1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of analyzing the effects of shadowing of halo implants performed on a transistor.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
However, reducing the channel length of a transistor also increases xe2x80x9cshort-channelxe2x80x9d effects. Short-channel effects include, among other things, an increased drain-source leakage current when the transistor is supposed to be switched xe2x80x9coff.xe2x80x9d This is a result of, at least in part, the source/drain depletion regions being closer together because of the shorter channel length. Short-channel effects also include xe2x80x9cthreshold voltage roll-offxe2x80x9d (i.e., the threshold voltage (Vth) decreases as gate length is reduced), and the like.
In general, short-channel effects may be reduced by using angled halo implants. Angled halo implants are implants of dopants that effectively xe2x80x9creinforcexe2x80x9d the doping type of the substrate in the channel between the source/drain extension regions (formerly known as lightly doped drain or LDD regions). For example, for an NMOS transistor, the doping type of the substrate in the channel between the N-type source/drain extension regions is a P-type dopant, e.g., boron (B) or boron difluoride (BF2). In this illustrative example, the halo implant process involves the use of P-type dopants implanted into the substrate at an angle (with respect to a direction horizontal to the surface of the substrate), and with a dose that may range from about 1.0xc3x971012 to 1.0xc3x971014 ions/cm2 at an implant energy ranging from about 5-15 keV for boron and about 20-70 keV for boron difluoride.
Similarly, for a PMOS transistor, the doping type of the substrate in the channel between the P-type source/drain extension regions is an N-type dopant, e.g., arsenic or phosphorous. For example, an angled halo implant comprised of arsenic (As) may be implanted into the substrate at an angle (with respect to a direction perpendicular to the surface of the substrate), and with a dose that may range from about 1.0xc3x971012 to 1.0xc3x971014 ions/cm2 at an implant energy ranging from about 40-70 keV for arsenic.
As shown in FIG. 1, for example, an illustrative field effect transistor 10 may be formed above a surface 15 of a semiconducting substrate 12, such as doped-silicon. The substrate 12 may be doped with either N-type or P-type dopant materials. The transistor 10 may have a doped-polycrystalline silicon (doped-polysilicon or doped-poly) gate electrode 14 formed above a gate insulation layer 16 that is formed above the surface 15 of the semiconducting substrate 12. The gate electrode 14 and the gate insulation layer 16 may be separated from doped source/drain regions 22 of the transistor 10 by dielectric sidewall spacers 20. The sidewall spacers 20 may be formed above shallow source/drain extension regions 24. Shallow trench isolation regions 18 may be provided to isolate the transistor 10 electrically from neighboring semiconductor devices such as other transistors (not shown).
A typical prior art process flow to produce the structure depicted in FIG. 1 will now be described. Initially, the trench isolations 18 are formed in the substrate 12. Thereafter, the gate insulation layer 16 and the gate electrode 14 are formed by forming the appropriate layers of material above the substrate 12, and thereafter patterning those layers by performing one or more etching processes to define the gate electrode 14 and the gate insulation layer 16. A masking layer 29, comprised of, for example, photoresist, is then formed above the substrate 12 and patterned to define an opening 21, thereby exposing the gate electrode 14 and the gate insulation layer 16. Next, halo implant regions 26 are formed. In particular, a halo implant process 25 is initially performed on one side of the device. Upon completion, the device may be rotated 180xc2x0 and the halo implant process 25 may then be repeated to form a halo implant region 26 on the opposite side. In practice, the device 10 may be subjected to four halo implants during processing. Four implants are typically performed because many of the transistors formed above a substrate are oriented approximately 90xc2x0 relative to one another.
Thereafter, a source/drain extension implant process (not shown) is performed to form the source/drain extension regions 24. Note that the implant process is typically self-aligned with respect to the gate electrode, although some small amount of scattering may occur. Thereafter, sidewall spacers 20 are formed adjacent the gate electrode 14. Then, a source/drain implant (not shown) is performed to form the doped region 28. This source/drain implant is generally aligned with respect to the sidewall spacers 20. Lastly, one or more anneal processes are performed to activate the implanted dopant atoms and to repair damage to the lattice structure of the substrate 12. During these anneal processes, the implanted dopant materials migrate, or diffuse, from their implanted location in a more or less isotropic fashion. The post-anneal positions of the various doped regions are depicted approximately in FIG. 1.
As shown in the illustrative NMOS device depicted in FIG. 1, Pxe2x88x92-doped regions 26 resulting from angled halo implants are typically provided adjacent the N-doped source/drain extension regions 24 to reduce some of the short-channel effects described above. In particular, by xe2x80x9creinforcingxe2x80x9d the P-doping type of the semiconducting substrate 12 in the channel between the N-doped source/drain extension regions 24, the laterally non-uniform Pxe2x88x92-doped angled halo implant regions 26 may improve the threshold roll-off (i.e., the threshold voltage (Vth) decreasing as gate length is reduced), thereby reducing short-channel induced effects such as a non-zero drain-source leakage current when the transistor is supposed to be switched xe2x80x9coff,xe2x80x9d (i.e., xe2x80x9coff-statexe2x80x9d leakage).
The angle 27 of the halo dopant implant 25 with respect to a line parallel to the surface 15 of the semiconducting substrate 12 may normally lie within a range of about 30xc2x0-60xc2x0. Typically, the semiconducting substrate 12 is tilted at the angle 27 with respect to a horizontal direction in an implanter (not shown) and the halo dopant is directed downward in a vertical direction. Alternatively, the semiconducting substrate 12 could be disposed in the horizontal direction in the implanter (not shown) and the halo dopant implant could be directed downward at the angle 27 with respect to the horizontal direction in the implanter, and/or any other combination of tilt and implant direction could be used as long as the angle 27 is the relative angle of the halo implant with respect to a line parallel to the surface 15 of the semiconducting substrate 12.
The halo dopants are implanted into and/or through a region of the substrate 12 that will eventually become the N-doped source/drain extension regions 24 of the device and the N+-doped regions 28. However, the dosage of the halo dopant atoms is typically at least an order of magnitude less than the dosage of dopant for the N-doped source/drain extension regions 24 and the doped regions 28. Similarly, the halo dopant atoms may also be implanted into the doped-poly gate electrode 14 and/or the gate insulation layer 16. However, the doping of the doped-poly gate electrode 14 also typically overwhelms the halo dopant atoms in the gate electrode 14. Furthermore, the amount of the halo dopant atoms in the gate insulation layer 16 is typically miniscule.
Typically, the dopant concentration used during the halo implant process may range from approximately 1.0xc3x971012 to 1.0xc3x971014 ions/cm2 of the appropriate dopant atoms, e.g., boron (B) or boron difluoride (BF2) for an illustrative NMOS transistor (the P-type halo implant serving to reinforce the P-type doping of the channel region of the NMOS transistor), or arsenic (As) or phosphorus (P) for an illustrative PMOS transistor (the N-type halo implant serving to reinforce the N-type doping of the channel region of the PMOS transistor). An implant energy of the halo dopant atoms and/or molecules may range from approximately 5-70 keV.
As discussed above, the masking layer 29 comprised of, for example, photoresist, is formed prior to performing the halo implant process 25. The opening 21 formed in the masking layer 29 exposes the transistor 10 to the halo implant process described above. However, as greater numbers of transistors are formed in a given plot space, the packing density of the transistors has increased dramatically. This, in turn, requires that an edge 31 of the opening 21 in the masking layer 29 be positioned increasingly closer to the sidewalls 19 of the gate electrode 14. However, as the masking layer 29 is positioned increasingly closer to the sidewalls 19 of the gate electrode 14, the masking layer 29 may block, or xe2x80x9cshadow,xe2x80x9d the halo implant process 25. Depending upon the degree of this shadowing, device performance may be adversely impacted. For example, the shadowing by the masking layer 29 may be so severe such that essentially none of the angled halo implant process is performed on the device 10. Alternatively, the shadowing may be such that the halo implant dosage is less than would otherwise be desirable. This shadowing may also result from an increased height in the masking layer 29. In any event, altering the effectiveness of angled halo implants by virtue of shadowing during the halo implant process can lead to adverse device performance, such as increased leakage when the transistor is not active, i.e., when the transistor is xe2x80x9coff.xe2x80x9d Additionally, shadowing of the angled halo implants may result in increased device capacitance, thereby slowing device performance.
The present invention is directed to solving, or at least reducing the effects of, some or all of the aforementioned problems.
The present invention is directed to a method of analyzing the effects of shadowing of angled halo implant processes performed on semiconductor devices. In one illustrative embodiment, the method comprises forming a plurality of transistors, each transistor having at least a gate electrode, and forming halo implant regions in the transistors while varying at least one of a halo implant angle, a masking layer height, and a lateral offset of a masking layer from the gate electrode of the transistors. The method further comprises determining electrical performance characteristics of at least some of the transistors where at least one of the halo implant angle, the masking layer height, and the lateral offset of a masking layer are different, and comparing the determined electrical performance characteristics of the transistors.